Multi-Core Computer Architecture | Week 6

Multi-Core Computer Architecture | Week 6

Course Links: https://onlinecourses.nptel.ac.in/noc23_cs113/course

Answers will be Updated soon!

Q1. Which one of the following statements is TRUE wrt a m-way set-associative cache memory organization?
Every cache block in a set will have a tag field.
There is only one tag field for each set.
Tag comparison happens sequentially from way 0 to way m-1.
Cache hit time will be dependent on way in which tag matching happens.

Q2. The word length of the processor is 16 bits.The address of the first byte of a word in a byte addressable 1 MB physical memory is 0xAB8F2. This word upon bringing to the cache is mapped to set 30. How many words can be accommodated in each cache block?
4
8
16
32

Q3. Consider a system with 8 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB with a word length of 16 bits. How many bits are required to represent the tag field in a cache block?
7 bits
5 bits
6 bits
3 bits

Q4. Which one of the following statements is TRUE for a write miss in no write allocate caches?
The block containing the missed word is brought to the cache for writing and will retain it there till it is evicted out.
Write the missed word in the main memory only.
Write the missed word in the main memory and then immediately bring the modified block to the cache.
The block containing the missed word is brought to the cache for writing and then immediately writes back the block to the main memory.

Q5. When a processor requests data from memory, the cache is checked first. Upon encountering a miss, the cache is loaded first from memory and then the processor is loaded from cache. This type of cache is called_____.
Look aside cache
Look through cache
Look inside cache
Look long cache

Q6. How many conflict misses are encountered when FIFO cache block replacement technique is used with a 4-way set associative cache for the following block access pattern? Assume initially the cache is empty.
P, Q, R, S, T, P, Q, S, R, T, Q, P
1
3
5
0

Q7. A program is stored in a 16 MB main memory that is attached to a 4 KB direct mapped D-cache with a block size of 16 bytes. The program reads 4 data words A, B, C and D in that order 5 times (total 20 memory references). Let the physical addresses of A, B, C and D are 0x420424, 0x74042A, 0x740664, 0x74066D, respectively. Assume the caches are empty initially and one word is 2 bytes. Which of the following statements is/are FALSE?
Out of the 20 memory references, 9 of them are cache hits.
Every access to D will be a hit.
At the end of 20 memory references, A, C and D are located inside the cache.
Every access to C will result in eviction of B from the cache.

Q8. The following 13 memory block requests A, B, D, A, B, C, E, A, B, E, D, C & D
are mapped to set n of a 4-way set-associative cache memory that uses Practical Pseudo LRU block replacement technique. Assume that set n is initially empty. What will be the contents of set n (in the order way0, way1, way2 and way3) after servicing all the requests? [Assume that data is entered into an empty cache block from way-0, way-1, way-2 & way-3 order]
ECDA
ECAD
EDCA
BEDC